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This is the Lecture Notes and Schedule for the Summer 2024 Semester

These links will take you to the specific week in the Schedule:

Anchor Links

These links will take you to the specific week in the Schedule:

[ Week 1 - June 3-9 ] [ Week 2 - June 10-16 ] [ Week 3 - June 17-23 ] [ Week 4 - June 24-30 ]

[ Week 5 - July 1-7 ] [ Week 6 - July 8-14 ] [ Week 7 - July 15-21 ] [ Week 8 - July 22-28 ]

[ Final Project Demonstration and Submission ]

Notes

Any changes to assignment due dates will be reflected on this page, announced in class, and posted to the Announcements page.
Part 1 of each lecture will be from 7:30pm - 8:40pm EST
There will be a 10 minute break each lecture
Part 2 of each lecture will be from 8:50pm - 10pm EST

Week	Date	Preview Reading	Lecture Materials	Lab, Homework and Project Assignments
Unit 1: Review of VLSI System Design Unit Objective: Students will review the fundamental CMOS devices, as well as design standard cells for use in future VLSI systems for both Analog and Digital devices.
1	Week 1 Learning Objectives Installation of Cadence Chamber and Completion of Muse/TSMC Non-Disclosure Agreement Review the fundamentals of CMOS Transistor Design Learn the Lambda-Design Rules that govern Design Rule Checks Translate logic into Gate Layouts and Stick Diagrams Physical Design and Standard Cells
	June 4	No Preview Reading Due	Part 1: Introduction to Advanced Integrated Circuits [ PPTX ] [ Zoom Video ] Part 1: MOS Transistors [ PPTX ] [ Zoom Video ]	Assignment 0 - Non-Disclosure Agreement Upload Due 6/4/24 at 11:59pm EST
	June 5	Reading 1-1: MOS Transistors and CMOS Logic Reading 1-2: Multiplexors, Transmission Gates, and Lambda-Design Rules	Part 1: Cadence Chamber Setup [ Appendix A - Non-Disclosure Agreement ] [ Cadence Chamber Setup Instructions ] [ Zoom ] Part 2: CMOS Logic and Lambda Design Rules [ PPTX ] [ Zoom Video ]	Lab 1 - Virtuoso Setup and Schematic Design Assigned: Wed, 6/5/24 Due: Fri, 6/7/24 at 11:59pm Sat, 6/8/24 at 11:59pm EST
	June 6	Reading 2-1: Gate Layouts Reading 2-2: Stick Diagrams Reading 2-3: Physical Design and Standard Cells	Part 1: Gate Layouts and Stick Diagrams [ PPTX ] [ Zoom Video ] Part 2: Physical Design and Standard Cells [ PPTX ] [ Zoom Video ]	Homework 1 - VLSI Circuit Design Review Assigned: Thu, 6/6/24 Due : Wed, 6/12/24 at 11:59pm EST
2	Week 2 Learning Objectives Review and strengthen our understanding of the impact of MOS Transistor Basics Calculate Noise Margins and Beta Ratio Effects Derive circuits using RC Delay Models, Elmore Delay Models and Linear-Delay Models Quantify the impact of these design choices on the power consumption and area of the circuit
	June 11	Reading 3-1: Circuit Design and MOS Transistor Basics Reading 3-2: Static CMOS Inverter Characteristics Reading 3-3: Noise Margins and Beta Ratio Effects	Part 1: Circuit Design and MOS Transistor Basics [ PPTX ] [ Zoom Video ] Part 2: Static CMOS Inverter Characteristics and Noise Margins [ PPTX ] [ Zoom Video ]
	June 12	Reading 4-1: Delay and Transient Response Reading 4-2: RC Delay Models Reading 4-3: Elmore Delay	Lab 2 - In-Class [ Place and Route ] [ Zoom Video 1 ] [ Zoom Video 2 ]	Lab 2 - Place and Route Assigned: Wed, 6/12/24 Due: Fri, 6/14/24 at 11:59pm
	June 13	Reading 5-1: Linear-Delay Models Reading 5-2: Parasitic Delay Reading 5-3: Logical Effort of Paths	Lab 2 - In-Class Continued [ Zoom Video ] Homework 2 Kick-OFF [ Zoom Video ]	Homework 2 - Simple Arithmetic Logic Unit Assigned: Thu, 6/13/24 Due : Tuesday, 6/18/24 at 11:59pm
3	Week 3 Learning Objectives Optimizing the number of stages in a VLSI circuit Calculate the Power Consumption of a IC Circuit
	June 18	Reading 6-1: Choosing the Best Number of Stages Reading 6-2: Power	Lab 3 - Analog Design using Virtuoso ADE Assembler [ Zoom Video 1 ] [ Zoom Video 2 ]	Lab 3 - Analog Design using Virtuoso ADE Assembler Assigned: Tue, 6/18/24 Due: Fri, 6/21/24 at 11:59pm
	June 19	No Preview Reading Assigned or Class Meeting in observation of Juneteenth Celebration Wednesday Office Hours Cancelled
	June 20	Reading 7-1: Static and Dynamic Power, and Switching Probabilities Reading 7-2: Clock Gating and Voltage Domains	Lab 3 - In-Class Continued [ Zoom Video ] Homework 3 Kick-OFF [ Zoom Video ]	Homework 3 - Analog Design of a Two-Stage Operational Amplifier Assigned: Thu, 6/20/24 Due : Wednesday, 6/26/24 at 11:59pm
Unit 2: Design Methodology and Project Proposals
4	Week 4 Learning Objectives Overview of Course Objectives Introduction to Verilog and RTL-to-GDSII Flow
	June 25		Lab 4: Part 1 [ Zoom Video ]	Lab 4 - (Re-)Introduction to Verilog Assigned: Mon, 6/25/24 Due: Fri, 6/28/24 at 11:59pm
	June 26		Lab 4: Part 2 [ Zoom Video ] Lab 4: Part 3 [ Zoom Video ]
	June 27		Lab 4: Part 4 - Flipped [ Zoom Video ]
5	Week 5 Learning Objectives Create Team Folder and Perform Homework 4 as a Team Go over Project Proposal Requirements Develop Project Proposal
	July 2		Part 1: Project Proposal - Verilog [ Schedule and Requirements ] [ Project Proposal Overview ] [ Zoom Video ]	Homework 4 - Simple ALU in Verilog Group Assignment Assigned: Tue, 7/2/24 Due : Wednesday, 7/3/24 at 11:59pm
	July 3		No Main Lecture Office Hours from 8-9pm EST (5-6pm PST)	Project Proposal Group Assignment Assigned: Tue, 7/2/24 Due : Friday, 7/5/24 at 11:59pm
	July 4	No Preview Reading Assigned or Class Meeting in observation of Independence Day No Thursday Office Hours
6	Week 6 Learning Objectives Time for Students to Work on Verilog and Synthesis Part 1 Presentation
	July 9		No Main Lecture Group Work Time
	July 10		No Main Lecture Group Work Time
	July 11		In-Class Project Review 1 [ Project Review 1 Deliverables ] [ Presentation 1 Video ]
Unit 4: Floorplanning and Verification Unit Objective: Generate a Valid Floorplan and GDS file using the Innovus Implementation System
7	Week 7 Learning Objectives Overview of Course Objectives Implementation of Floorplanning using Innovus Implementation System Adding IO Pads to our circuit
	July 16		Lab 5 - Part 1 [ Part 1 ] [ Zoom Video ]
	July 17		Lab 5 - Part 2 and 3 [ Part 2 ] [ Zoom Video ]
	July 18		In-Class Project Review 2 [ Project Review 2 Deliverables ] [ Presentation 2 Video ]
8	Week 8 Learning Objectives Distributing multiple power pins around the chip IO Fill Cells and IO Bond Pad Placement Use of Decoupling Capacitors to reduce Noise Power Routing
	July 23		Part 1: Multiple Power Pins [ Lab 6 - Part 1 ] [ Zoom Video ]
	July 24		Part 1: IO Placement [ Lab 6 - Part 2] [ Zoom Video ] Part 2: Generating the Final GDS File [ Lab 6 - Part 3 ] [ Zoom Video ]
	July 25		In-Class Project Review 3 [ Project Review 3 Deliverables ] [ Presentation 3 Video ]
Final Project Demonstration and Submission Date: Demonstration During Final Exam Time Period * Rest of the University's Final Exam Schedule may be found here - [ Howard University Final Exam Schedule ]